This invention extends a high level description language so that single or multi-channeled real values, electrical signals, or a combination may be passed on model ports. In this patent application, this capability is referred to as analog wires. The term, dgWires, is synonymous with analog wires. The invention also adds other capabilities to facilitate analog, mixed-signal, radio-frequency (RF) modeling such as extending the language to provide math functions suitable for writing these models. The invention will typically be used by an engineer to assist in the design of an electrical system such as an integrated circuit or system of integrated circuits and electrical components on a printed circuit board.
At the core of an analog, mixed-signal, or RF design are blocks or subcomponents of the design that communicate by transmitting information on wires from one block to another. Many languages are available for modeling and writing regression tests. The two languages most suited to modeling analog are Verilog-AMS and VHDL-AMS. Simulators that can handle these languages require both a digital event-driven simulation engine and an analog or circuit ordinary differential equation solver engine. The latter is generally known as a SPICE engine or analog simulator. A SPICE engine requires solving a network of simultaneous equations. Simulators that have both an event-driven simulation engine and SPICE engine or generally known as AMS simulators. There are two primary disadvantages when using an AMS simulator over only a pure digital event-driven simulator. The first disadvantage is simulation speed. A SPICE engine typically runs slower than a digital event-driven simulator. As a result, when simulating a design, the combination of the two simulators runs slower than the digital event-driven simulator. The second disadvantage is cost. Because both simulation technologies are required for an AMS simulator, vendors of simulators charge a premium for the AMS simulator. Because of these disadvantages, analog design and verification engineers have attempted to only apply digital event-driven simulators to model analog, mixed-signal, and RF designs. However, because the digital event-driven simulators were not intended to model analog designs, there are limitations to what may be done. Specifically, one of the most prevalent modeling languages for digital design is Verilog. A key stumbling block to Verilog is that continuous-valued signals, e.g. real numbers, cannot be passed from a design block (module) to another. U.S. Pat. No. 7,260,792 to Chandrashekar L. Chetput, Ramesh S. Mayiladuthurai, and Prasenjit Biswas (2007) and U.S. Pat. No. 7,251,795 to Prasenjit Biswas, Ramesh S. Mayiladuthurai, Chandrashekar L. Chetput, and Abhijeet Kolpekwar (2007) describe methods for passing signals in a mixed-language, mixed-signal design where both a digital event-driven simulation engine and a SPICE engine is required.
To work around this problem in Verilog, engineers have attempted to develop methods by which to pass real numbers between blocks. Initial attempts focused on staying within the Verilog language. They include converting a real number to a 64 bit bus using the $realtobits and $bitstoreal command. This has the disadvantage that it changes the interface of the block from 1 wire to 64 wires. This is usually unacceptable. Another method is to use out of module references to real variables inside the block. This has the disadvantage that one has to know the name of the sender block in order to be able to access the information that is being transmitted. The name of the block is usually not known by adjacent blocks and thus, this is also not workable as a solution. Another method is to convert the 64 bits into a serial stream of data transmitted across the port. This has the disadvantage in that it may slow down the simulation and there is coding overhead to set up the transmitters and receivers to code and decode the data. Similar to this is to use pulse width modulation techniques to indicate the value of the real variable. This again has a disadvantage of requiring a coder and decoder. None of these solutions have been satisfactory as designers and verification engineers sought other solutions. The next set of solutions look toward different languages. VHDL allows the passing of real variables between blocks. The disadvantage of using VHDL is that Verilog is a much more popular language. As a result, it is difficult to find engineers who have the knowledge to program in VHDL and companies are reluctant to convert all of their models to VHDL fearing that their models will be forever incompatible with the more popular Verilog language. Another choice is to use Verilog-AMS, but not write models in such a way that use the SPICE simulator but take advantage of a “wreal” port type which is a wire which carries a real value. This still has the cost disadvantage. The “wreal” port type also does not have all of the capabilities required for analog modeling. Finally, a newer language is SystemVerilog which allows for real valued ports. The disadvantage here is that it is a newer language, and so fewer engineers know how to use it, but more significantly, at present it is not compatible with either of the AMS languages as there are no AMS extensions to SystemVerilog. The significance of this limitation is apparent when it comes time to verify that an analog model, which is generally manually generated, matches the corresponding circuit. The model has to be validated by a regression test that may simulate and compare against the transistor level implementation. Thus, the language used by the regression test has to be compatible with the modeling language. The SystemVerilog also does not have all of the capabilities required for analog modeling.
Besides passing a single real value between one block to another, there are other capabilities required for analog modeling. These requirements include the need to pass more than one real number across a signal a wire. Another capability is the need to turn on and off the pin or port on the block to support analog buses. There is a need to show the state of the connecting wire, whether or not there is contention or whether or not there is a signal driving the wire. Finally, there is the need to represent some electrical sources, such as voltage and current sources. It is very common to need to sum current sources, or check voltage source values. Seeing the loading effects are also important. There are efficiency concerns in implementing any solution that provides this capability as simulation speed is one of the reasons for using a digital event-driven language. Finally, when adding this capability, they have to be added in such a way that they are compatible with the key commercial simulators that designers and verification engineers are using. Often, a company will use more than one. Thus, models that are created must work in all of them and behave the same. It may also be the case that these event-driven models need to be connected to a model written in Verilog-AMS. One feature of the Verilog-AMS language is that connect modules may be written to connect electrical signals from the Verilog-AMS languages to logic signals in Verilog. For these analog wires, a requirement is that real values may be connected to Verilog-AMS using a connect module, so that analog signals may pass from an event-driven model to an analog simulator.
To support analog modeling, other capabilities are required, the Verilog language is limited in the math function it provides. Extensions need to be provided for these, and any capability added to the language needs to include some debugging aids to help debug issues as the designers and verification engineers write the models.
Having exhausted all of the standard languages, an alternative is to extend the language to provide the capabilities required. In US Patent Application Publication 2002/0049576 by Steven J. Meyer (published 2002), a system is described to extend the capabilities of an event-driven simulator, however, an analog simulator is still required. “Functional Verification in the Presence of Linear Analog Circuits” by Thomas J. Sheffler presented at the Design and Verification Conference in 2008, and “Design of a Switch-Level Analog Model for Verilog” by Thomas J. Sheffler presented at the IEEE International Behavioral Modeling and Simulation Conference in 2008 also describe extensions to an event-driven simulator to facilitate analog modeling. These extensions also require that a simultaneous set of equations be solved. Finally, “Sending Analog Values Along Digital Wires” by Chris S Jones, Jeff McNeal, and Ross Segelken presented at the Design and Verification Conference in 2007 describes a Verilog extension to pass analog values between Verilog models, but in this solution, important capabilities such as the ability to indicate whether or not a port is driven are not provided.